 本文转载自BRIAN BAILEY发表在SEMICONDUCTORENGINEERING上的文章 The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs. 机器翻译（仅供参考）：嵌入式FPGA是集成在ASIC或SoC中的IP核，其正在发生转变。 系统架构师开始意识到eFPGA的优势，它提供了可编程逻辑的灵活性，而无需FPGA的成本。 Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they need to launch products they know will need frequent updating. 机器翻译（仅供参考）：可编程逻辑特别适合于加速需要频繁更新的机器学习应用程序。 eFPGA可以为一些架构师提供他们知道需要频繁更新的产品所需的覆盖。 Field programmable gate arrays (FPGAs) traditionally were considered too expensive for most applications and often relegated to prototypes or providing a time-to-market advantage for emerging standards. But the economics are changing. Integrating a reprogrammable fabric into an SoC is increasingly seen as a viable and valuable option. 机器翻译（仅供参考）：传统上，现场可编程门阵列（ FPGAs ）对于大多数应用而言过于昂贵，通常被降级为原型或为新兴标准提供上市时间优势。 但经济正在发生变化。 将可重新编程的结构集成到SoC中越来越被视为一种可行且有价值的选择。 “With an eFPGA, you define the quantity of look-up-tables (LUTs), registers, embedded memory, and DSP blocks. You can also control the aspect ratio, number of I/O ports, making tradeoffs between power and performance,” says Kent Orthner, systems architect at Achronix. “At the same time, the industry is embracing heterogeneity. You need different blocks that are good for different things. So you may have a secure block, and this is a place where eFPGAs play well. They can be specialized, but you don’t have to keep it that way.” 机器翻（仅供参考）：“使用eFPGA，您可以定义查找表（LUT），寄存器，嵌入式存储器和DSP模块的数量。 您还可以控制宽高比，I / O端口数量，在功耗和性能之间进行权衡，“ Achronix的系统架构师Kent Orthner说。 “与此同时，该行业正在接受异质性。 你需要不同的块来满足不同的需求。 所以你可能有一个安全的区块，这是一个eFPGAs发挥良好的地方。 它们可以是专业的，但你不必保持这种方式。“  图1：具有可编程加速度的SoC。 资料来源：Achronix That changes the economics of FPGA technology. “For many years [programmable logic] was very expensive,” says Joe Mallett, senior product marketing manager for FPGA-based synthesis software tools at Synopsys. “The cost per LUT was high, and to get a usable amount of combinational logic on the silicon was too expensive. The inflection point was somewhere around 40nm, and then the cost per LUT became low enough that you can put enough logic on the SoC or ASIC that it makes sense.” 机器翻译（仅供参考）：这改变了FPGA技术的经济性。 “多年来[可编程逻辑]一直非常昂贵，” Synopsys基于FPGA的综合软件工具高级产品营销经理Joe Mallett说。 “每个LUT的成本很高，并且在硅片上获得可用数量的组合逻辑太昂贵了。 拐点大约在40nm左右，然后每个LUT的成本变得足够低，你可以在SoC或ASIC上放置足够的逻辑，这是有道理的。“ It has been more than a decade since 40nm was first introduced. “It takes time between when architects have a new tool to consider and manage to wrap their heads around it,” says Geoff Tate, CEO at Flex Logix. “Five years ago, embedded FPGA became available. [Architects] never had the opportunity to think about it before then. Over time, with education and understanding, and demonstration that the technology is viable and ready for production, we are seeing architects figuring out how to make best use of the embedded FPGA.” 机器翻译（仅供参考）：自40nm首次推出以来已有十多年了。 Flex Logix首席执行官Geoff Tate说：“架构师需要时间来设计一个新的工具，并设法绕过它。” “五年前，嵌入式FPGA成为可用的。 [架构师]在此之前从未有机会考虑它。 随着时间的推移，通过学习和理解，证明该技术是可行的并且可以用于生产，我们看到架构师正在研究如何充分利用嵌入式FPGA。“ Several characteristics and trends make eFPGAs appealing now:
机器翻译（仅供参考）：现在有几个特征和趋势使eFPGA具有吸引力：
Product flexibility 产品灵活性 Few people claim that the traditional Moore’s Law still applies to most product development. “For a significant number of designs, you don’t need all of the advances of 7nm,” says Frank Schirrmeister, senior group director for product management and marketing at Cadence. “For them, the lesser nodes may be sufficient, and with that the flexibility of an FPGA embedded into an SoC is good.” 机器翻译（仅供参考）：很少有人声称传统的摩尔定律仍适用于大多数产品开发。 “对于多数的设计，你完全不需要7nm技术，” Cadence产品管理和营销高级组主管Frank Schirrmeister说。 “对于他们来说，较小的节点可能就足够了，因此嵌入SoC的FPGA的灵活性很好。” The programmability of eFPGAs enables IC functionality to be changed on the fly after chip development is complete. “This enables a single IC to address a diverse set of use cases and adapt to changing requirements instead of forcing development of another ASIC,” adds Brian Mathewson, verification technologist for Mentor, a Siemens Business. “Incorporating a programmable logic fabric may have a penalty in terms of power, performance and design cost compared with the same logic implemented in traditional gates. This drives a tradeoff between cost and flexibility for a target application.” 机器翻译（仅供参考）：eFPGA的可编程性使芯片开发完成后可以即时更改IC功能。 “这使得单个IC能够解决各种用例并适应不断变化的需求，而不是强制开发另一个ASIC，” 西门子事业部门Mentor的验证技术专家Brian Mathewson补充道。 “与传统门中实现的相同逻辑相比，结合可编程逻辑结构可能在功率，性能和设计成本方面受到损害。 这推动了目标应用的成本和灵活性之间的权衡。” But sometimes traditional gates make little sense. “If we consider serial I/O, there are many relevant standards and people would like to have the flexibility to implement all of them,” says Flex Logix’s Tate. “But you don’t have to have the entire serial I/O go into eFPGA. Large portions of it remain the same for all of the standards.” 机器翻译（仅供参考）：但有时传统方法毫无意义。 “如果我们考虑串行I / O，有许多相关标准，人们希望能够灵活地实现所有这些标准，”Flex Logix的Tate说。 “但你不必让整个串行I / O进入eFPGA。 对于所有标准，它的大部分都保持不变。”  图2：Flex Logix的推理芯片架构，具有可重新配置的数据路径。 Tobias Welp, engineering manager for OneSpin Solutions, agrees. “Programmable I/O is a popular application. In addition to product variations, it fosters the use of new interface standards that may still have issues to be resolved and additional features planned for future revisions.” 机器翻译（仅供参考）：OneSpin Solutions的工程经理Tobias Welp对此表示赞同。 “可编程I / O是一种流行的应用程序。 除了产品变化之外，它还促进了新接口标准的使用，这些标准可能仍有待解决的问题以及为未来修订计划的其他功能。” Increasing market size makes good sense. “Markets that are fragmented, and thus have modest unit volumes, are well suited for eFPGA deployment as a single SoC can target multiple use cases by customizing the logic on the eFPGA,” says Himanshu Sanghavi, senior director of engineering for programmable IP for Quicklogic. “One such a market is IoT. While the total market is very high volume, many sub-segments are within the umbrella of IoT, ranging from home automation to wearable devices to a variety of smart sensors. Each of these segments has specific requirements that are different from use cases in the other segment(s).” 机器翻译（仅供参考）：增加市场规模是有道理的。 “由于单个SoC可以通过定制eFPGA上的逻辑来定位多个用例，因此市场分散，具有适度的单位体积，非常适合eFPGA部署，”Quicklogic可编程IP工程高级主管Himanshu Sanghavi说道。 。 “一个市场是物联网 。 虽然整个市场的销量非常高，但许多子细分市场都属于物联网领域，从家庭自动化到可穿戴设备，再到各种智能传感器。 这些细分中的每一个都有特定要求，与其他细分市场中的用例不同。” Performance 性能 Machine learning is adding some new requirements into products. “FPGA fabric may be added to SoCs to enable variations in the engines and processors with domain-specific instruction sets,” points out OneSpin’s Welp. “In some cases, it may be possible to map algorithms for machine learning and other key applications into hardware and later refine the design as the results improve.” 机器翻译（仅供参考）：机器学习为产品增加了一些新的要求。 “可以在SoC中添加FPGA架构，以便通过特定领域的指令集实现引擎和处理器的变化，”OneSpin的Welp指出。 “在某些情况下，有可能将机器学习和其他关键应用程序的算法映射到硬件中，然后随着结果的改进而改进设计。” SoC designers are constantly evaluating performance and flexibility tradeoffs between competing solutions for their application. “On one end of the spectrum, general-purpose programmable processors offer the greatest amount of flexibility via software, while at the other end of the spectrum, custom fixed-function blocks designed in RTL offer the best power/performance characteristics,” says Quicklogic’s Sanghavi. “FPGAs sit somewhere in between, offering better power/performance than a general-purpose CPU, and more flexibility than fixed function RTL. As a result, embedded FPGAs are most suitable for SoC design tasks, for which some amount of post-silicon programmability is a must, yet a pure software solution does not meet the performance or power goals of the application.” 机器翻译（仅供参考）：SoC设计人员不断评估其应用竞争解决方案之间的性能和灵活性权衡。 “在频谱的一端，通用可编程处理器通过软件提供最大的灵活性，而在另一端， RTL设计的定制固定功能块提供最佳的功率/性能特性，”Quicklogic的说法桑海维。 “FPGA介于两者之间，提供比通用CPU更好的功率/性能，比固定功能RTL更灵活。 因此，嵌入式FPGA最适合SoC设计任务，其中一些后硅可编程性是必须的，但纯软件解决方案不能满足应用的性能或功耗目标。 Reduced integration costs 降低集成成本 Mainstream FPGA providers have been integrating increasing amounts of functionality into their devices for a long time, making them SoCs with a large amount of reprogrammable fabric. “FPGA vendors now offer high-end devices that fully qualify as SoCs, including CPUs, specialty engines and large memories,” says Welp. “Conversely, SoC developers now have the ability to embed FPGA fabric into their designs to provide a high level of flexibility. Either type of chip can be called a heterogenous computing platform with a rich mixture of fixed processors, programmable engines, programmable logic and memory.” 机器翻译（仅供参考）：主流FPGA供应商长期以来一直在将越来越多的功能集成到他们的设备中，使其成为具有大量可重编程结构的SoC。 “FPGA供应商现在提供完全符合SoC标准的高端设备，包括CPU，专业引擎和大型存储器，”Welp说。 “相反，SoC开发人员现在能够将FPGA架构嵌入到他们的设计中，以提供高度的灵活性。 任何类型的芯片都可以称为异构计算平台，具有固定处理器，可编程引擎，可编程逻辑和存储器的丰富组合。” But there is an important difference. “Traditional FPGAs had some high-level fixed blocks and they were expecting the customer to be able to use some of those,” says Yoan Dupret, managing director and vice president of business development for Menta, an embedded programmable logic company. “The major difference between FPGAs and embedding an FPGA fabric into an SoC is that you don’t consider it a blank sheet of paper where you can do whatever you want with the eFPGA. One way to improve power/performance/area (PPA) tradeoffs is to restrict the architectures that you will use, and that is not hard because your ASIC or SoC is already restricting the number of applications that they will have.” 机器翻译（仅供参考）：但是有一个重要的区别。 “传统FPGA有一些高级固定模块，他们希望客户能够使用其中的一些，”嵌入式可编程逻辑公司Menta的业务开发总经理兼副总裁Yoan Dupret说。 “FPGA与将FPGA架构嵌入SoC之间的主要区别在于，您不认为它是一张白纸，您可以使用eFPGA做任何您想做的事情。 改善功耗/性能/面积（ PPA ）权衡的一种方法是限制您将使用的架构，这并不难，因为您的ASIC或SoC已经限制了它们将拥有的应用程序的数量。 Security 安全 Security is becoming an increasing concern for connected products. “The eFPGA allows developers to have the flexibility to do things such as to change security protocols and adapt their chips to changing markets and customer needs,” says Tate. “Given how expensive it is to design a chip, anything you can do to extend the chip’s useful life, and breadth of application will improve your return on investment.” 机器翻译（仅供参考）：安全性正成为互联产品日益受到关注的问题。 “eFPGA允许开发人员灵活地做一些事情，例如改变安全协议并使他们的芯片适应不断变化的市场和客户需求，”Tate说。 “考虑到设计芯片的成本有多高，你可以做任何事情来延长芯片的使用寿命，应用范围也会提高你的投资回报率。” This is particularly important in applications where chips are expected to last a decade or more, such as in automotive or industrial markets. Security measures implemented today will likely not be considered as secure in a decade. 机器翻译（仅供参考）：这在芯片预计可持续十年或更长时间的应用中尤为重要，例如汽车或工业市场。 今天实施的安全措施可能在十年内不被认为是安全的。 Extended life, changing economics 延长寿命，改变经济状况 Product life can also be extended for deployed products. “The flexibility of the eFPGA helps extend the time-in-market for the SoC, as new use cases that become known well after the SoC has gone into production can be addressed through the use of the eFPGA,” says Sanghavi. “The embedded FPGA provides area, power and cost benefits over the two-chip solution.” 机器翻译（仅供参考）：部署产品的产品寿命也可以延长。 “eFPGA的灵活性有助于延长SoC的上市时间，因为在SoC投入生产后熟知的新用例可以通过使用eFPGA来解决，”Sanghavi说。 “嵌入式FPGA提供了超过双芯片解决方案的面积，功耗和成本优势。” This may enable new business models to be developed such that additional capabilities could be added to deployed products, changing the business model from a pure sales model to a service model. 机器翻译（仅供参考）：这使得能够开发新的商业模型，使得可以向部署的产品添加附加功能，从而将商业模型从纯销售模型改变为服务模型。 In addition, eFPGAs can have a fundamental impact on the entire design process. Rather than developing another chip with new IP, the same chip can be updated or even applied to new markets. 机器翻译（仅供参考）：此外，eFPGA可以对整个设计过程产生根本性影响。 而不是开发具有新IP的另一芯片，相同的芯片可以更新或甚至应用于新市场。 “The cost of derivatives is becoming more important as the cost of developing chips goes up,” says Achronix’s Orthner. “You want to get as much bang for your buck. This allows you to spread the NRE for an ASIC across a multitude of different functions and markets. You can develop one chip and sell it as a dozen different parts.” 机器翻译（仅供参考）：“随着开发芯片的成本上升，衍生产品的成本变得越来越重要，”Achronix的Orthner说。 “你希望得到更多的回报。 这使您可以在众多不同的功能和市场中为ASIC分发NRE。 你可以开发一种芯片并将其作为十几种不同的部件出售。” This approach can span everything from SoCs to microcontrollers, which have long been used for products that require software flexibility. 机器翻译（仅供参考）：这种方法可以涵盖从SoC到微控制器的所有方面，这些方法长期以来一直用于需要软件灵活性的产品。 “Today, almost all our customers program the FPGA themselves,” says Tate. “If you are going to build and sell a chip where the customer will program it, it opens up a bunch of support and business questions. Companies want to build a chip where they do the programming, to make sure they fully understand all of the issues in the hardware and software and where they can control everything first. Then they can look at the next step, which is letting the customers program it.” 机器翻译（仅供参考）：“今天，几乎所有客户都自己编程FPGA，”Tate说。 “如果您要在客户编程的地方构建或销售一个芯片，那么就会产生一系列支持和业务问题。 公司希望在他们进行编程的地方构建一个芯片，以确保他们完全理解他们首先控制的硬件和软件中的所有问题。 然后他们可以考虑下一步，即进行编程。“ Architectural considerations 架构考虑 Integrating an eFPGA fabric can be done in several ways, but careful consideration has to be given to the intended application. “There are two primary integration types,” says Synopsys’ Mallett. “One is being used as an accelerator and can do some heavy lifting in processing and the other is more of potential bugs fixes or silicon configuration or secret sauce that will not become publicly visible. These are different use cases for the eFPGA. For heavy acceleration, where it will be used for accelerating functionality, it is closer to the idea of the standalone chips with an embedded processor, but with a smaller fabric amount.” 机器翻译（仅供参考）：可以通过多种方式集成eFPGA结构，但必须仔细考虑预期的应用。 “有两种主要的集成类型，”Synopsys的Mallett说。 “一个被用作加速器，可以在处理中做一些繁重的工作，另一个是更多的是修复潜在的错误或硅配置，不会公开可见。 这些是eFPGA的不同用例。 对于重型加速，它将用于加速功能，更接近带嵌入式处理器的独立芯片的想法，但结构数量更少。” Without due consideration, integration may lead to disappointing results. “Architects need to understand the tradeoffs and how to get the most advantage out of an eFPGA with the least penalty,” says Tate. “People start thinking about how great it is to have flexibility, but then they try to take a giant block of the chip and put it into an eFPGA. They end up finding that it is too big and expensive. The architects have to figure out how to use it. They must examine the RTL and figure out which portions need to be flexible and which portions can remain in hardwired logic. They have to partition the architecture, which takes some work and thinking about. They should put as little as possible of their architecture into flexible eFPGA in order to minimize the area cost, but still get the required amount of flexibility.” 机器翻译（仅供参考）：如果没有适当的考虑，整合可能会导致令人失望的结果。 “架构师需要权衡，以及如何以最少的代价从eFPGA中获得最大优势，”泰特说。 “人们开始考虑拥有灵活性是多么重要，但随后他们试图将一块巨大的芯片放入eFPGA中。 最终发现它太大而且太昂贵。 架构师必须弄清楚如何使用它。 他们必须检查RTL并找出哪些部分需要灵活，哪些部分可以保留在硬连线逻辑中。 他们必须对架构进行划分，这需要一些工作和思考。 他们应尽可能少地将其架构放入灵活的eFPGA中，以最大限度地降低面积成本，但仍能获得所需的灵活性。” Sizing of the fabric is critical. “There are a couple of different ways to approach this problem,” says Sanghavi. “If the SoC designer has a good idea of the hardware they plan to map to the embedded FPGA, they can use the tools provided by the vendor to decide on the size of the fabric. Alternatively, in many instances SoC designers are using an embedded FPGA because they are not sure what hardware will need to go on it over the life of the IC, and there is the need to amortize the high SoC design cost across multiple system designs. In this situation, it is best to use the largest eFPGA that will still meet the die size budget of the SoC. The larger the fabric, the more post-silicon flexibility it will provide.” 机器翻译（仅供参考）：结构的尺寸是至关重要的。 “有几种不同的方法可以解决这个问题，”Sanghavi说。 “如果SoC设计人员对他们计划映射到嵌入式FPGA的硬件有一个很好的了解，他们可以使用供应商提供的工具来决定结构的大小。 或者，在多数情况下，SoC设计人员使用嵌入式FPGA，因为他们不确定在IC的整个生命周期中需要使用哪些硬件，需要在多个系统设计中分摊高SoC设计成本。 在这种情况下，最好使用仍能满足SoC芯片尺寸预算的eFPGA。结构越大，它提供的灵活性就越大。” That can be a fine line. “eFPGAs can vary in size depending on the function they are serving,” adds Mentor’s Mathewson. “Additional flexibility built into today’s SoCs can always be useful, but there are impacts to building this flexibility in. It is critical to bound your potential design space up front.” 机器翻译（仅供参考）：这可能是一个很好的路线。 “eFPGAs的大小可以根据他们所服务的功能而变化，”Mentor的Mathewson补充道。 “今天的SoC内置的额外灵活性总是很有用，但是要在这方面建立这种灵活性会产生影响。预先设置潜在的设计空间至关重要。” This will vary depending upon the end market. “If you look at the person who has an FPGA with fixed components around it, you have specific product categories, such as a large device with lots of FPGA, because you have video and processing pieces to be mapped into it, whereas others may have a smaller FPGA portion,” says Cadence’s Schirrmeister. “You figure out for the FPGA how much data access you need to provide the I/O bandwidth, you figure out the processing need, and that determines speed and size. And you do this with some example applications.” 机器翻译（仅供参考）：这取决于最终市场。 “如果你看一下拥有固定组件的FPGA的人，你就会有特定的产品类别，例如带有大量FPGA的大型设备，因为你有视频和处理部分要映射到它，而其他人可能有较小的FPGA部分，“Cadence的Schirrmeister说。 “你需要为FPGA提供提供I / O带宽所需的数据访问量，你需要确定处理需求，确定速度和大小。 你可以用一些示例应用程序来做到这一点。” The problem is similar to sizing memory for software. “You can never have enough software memory, but that doesn’t mean you can afford what you may like,” says Tate. “We provide tools that can determine, for various RTL, how big the array needs to be and how fast it will run. Then they have to make a judgment, because you never know what may happen in the future and how much bigger my RTL might become.” 机器翻译（仅供参考）：问题类似于为软件调整内存大小。 “你永远不会拥有足够的软件内存，但这并不意味着你能负担得起你想要的东西，”泰特说。 “我们提供的工具可以确定，对于各种RTL，阵列需要多大以及运行速度有多快。 然后他们必须作出判断，因为你永远不知道将来会发生什么，以及我的RTL会变得多大。” What judgment do people use today? “Once a customer has worked out what they need for a handful of representative applications, then can size the resources they require,” says Menta’s Dupret. “They might increase those resources by a fixed amount. Some might go with 10% while other may go up to 50%. It is really a guess today.” 机器翻译（仅供参考）：人们今天用什么判断？ “一旦客户找到了他们对少数代表性应用的需求，就可以调整他们所需的资源，”Menta的Dupret说。 “他们可能会将这些资源增加一定数额。 有些可能会达到10％，而有的可能达到50％。 现在还不好说。” Power management 电源管理 Power reduction is important, but when considering a flexible resource such as eFPGA, it becomes even more difficult. “All transistors leak unless you put in power gating, which also has a cost,” says Tate. “For some applications, typically 40nm and above, power is very critical, and they are looking to include a power-gating function. Generally, at 28nm and 16nm, people are more focused on speed, and power gating cuts into performance.” 机器翻译（仅供参考）：降低功耗很重要，但在考虑eFPGA等灵活资源时，它变得更加困难。 “所有晶体管都会泄漏，除非你进行电源门控，这也需要成本，”泰特说。 “对于某些应用，通常为40nm及以上，功率非常关键，他们希望包括功率门控功能。 一般来说，在28nm和16nm，人们更注重速度，而功率门控会降低性能。” Power gating also leads to synthesis complications. “When you look at SoCs, you have the ability to turn on and off blocks depending on usage needs,” says Mallett. “There is a lot more independent power control. When you combine FPGA into an SoC, it is likely to be turned on and off, programmed and reprogrammed, so you have to be aware of those possibilities. You have to be aware of how you are programming the block and how it relates to the system. For synthesis, I may have multiple power domains in an FPGA that I need to take care of and know what that means. That may change the way I am doing the design because if you cross power domains, you have to make sure that the right pieces are powered up.” 机器翻译（仅供参考）：功率门控也会导致合成并发症。 “当你看到SoC时，你可以根据使用需求打开和关闭块，”Mallett说。 “还有更多的独立电源控制。 当您将FPGA组合到SoC中时，它很可能会被打开和关闭，编程和重新编程，因此您必须了解这些可能性。 您必须了解如何对块进行编程以及它与系统的关系。 对于合成，我可能在FPGA中有多个电源域，我需要注意并知道这意味着什么。 这可能会改变我进行设计的方式，因为如果您跨越电源域，则必须确保正确的部件已通电。” The important tradeoff is the amount of energy consumed for a specified function. “When you are working on an application that is very sensitive to power consumption, like an IoT application, the size of the eFPGA is usually much smaller and the number of applications it is to be used for is more limited,” says Dupret. “They don’t need to have as much expansion room. But on the other side, architects must get out of the mindset that eFPGA will always take a lot of space and power, because there may be a lot of instances where this is not the case. It may even be more area-efficient or power-efficient than other solutions.” 机器翻译（仅供参考）：重要的权衡是特定功能所消耗的能量。 “当您处理对功耗非常敏感的应用程序时，例如IoT应用程序，eFPGA的功耗通常要小得多，而且它的应用程序数量会更加有限，”Dupret说。 “他们不需要拥有那么多的扩展空间。 但另一方面，架构师必须摆脱eFPGA总是会占用大量空间和能量的思维定式，因为可能会有很多情况并非如此。 它甚至可能比其他解决方案更具区域效率或能效。” This adds a level of complexity to product development. “As integration continues to increase, programming models become more complex,” says Max Odendahl, CEO at Silexica. “Engineers now need to consider how the application is distributed across the processing elements and FPGA fabric and know how to program each element. System-level memory dependencies and cache coherency must also be considered in the design process. EDA tool vendors will need to keep pace and provide utilities that help simplify the programming model.” 机器翻译（仅供参考）：这增加了产品开发的复杂程度。 “随着集成度的不断提高，编程模型变得更加复杂，”Silexica首席执行官Max Odendahl 表示 。 “工程师现在需要考虑应用程序如何在处理元件和FPGA架构中分布，并知道如何对每个元素进行编程。 在设计过程中还必须考虑系统级内存依赖性和高速缓存一致性。 EDA工具供应商需要跟上步伐并提供有助于简化编程模型的实用程序。” IC智库 你的网络导师 ○ IC智库APP ○ 动态 | 视频 | 专家 | 教育   扫码下载 或打开www.iczhiku.com 记得这是一个有深度的公众号  ●深度调查：中国IC设计公司将要迎来显著的销售增长 ---------------------------------------------------------------------------------------------------------------------- 我们尊重原创，也注重分享，文章来源于微信公众号：IC智库，建议关注公众号查看原文。如若侵权请联系qter@qter.org。 ---------------------------------------------------------------------------------------------------------------------- |
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